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DV Engineer - 6 month contract
Digital Verification Engineer - Contract This role does not provide sponsorship We are a semiconductor startup driven to advance the frontier of reasoning and reliability in the real world. At the center of our mission is bridging artificial intelligence to the most sensitive industrial and advanced manufacturing applications around the globe. We are tackling these problems with a mix of interdisciplinary approaches across the full stack, from probabilistic software infrastructure and algorithms to hardware and physics. As a Digital Verification Engineer, you will bring your expertise in the end to end design verification flow for functional coverage by supporting our Verification AI team and building testbench environments from design documents to support product development. Overview & Responsibilities Remote 6 month contract 40 hours per week Temp hire or C2C Building test benches from scratch Partnering with our internal hardware, product, and machine learning teams Basic Qualifications 5+ years of experience in Digital Verification at a major semiconductor company Experience working on DRAM, Memory Controllers, ASICS, or MCUs Proven expertise in all areas of the end to end design verification workflow for function coverage, including design document review, feature extraction, test plan creation, stimulus generation, testbench creation, and test suite creation Advanced proficiency in SystemVerilog and UVM Methodology Proficiency with EDA verification tools like vManager, Xcelium, Jasper, etc. Experience in creating and testing with Verification IPs Excellent written and spoken communication skills Preferred Qualifications: Bachelor’s or Master’s degree in Computing Engineering, Electrical Engineering, or a related field Experience in SystemC Experience in formal verification