PowerPC 603e Test Development

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We're looking to develop a test program to test P/N: TSPC603RMABQ8LC. Device Information: The PID7t-603e implementation of the PowerPC 603e (renamed after the 603R) is a low-power implementation of the Reduced Instruction Set Computer (RISC) microprocessor PowerPC family. The 603R is pin-to-pin compatible with the PowerPC 603e and 603P in a Cerquad package. The 603R implements 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. The 603R is a low-power 2.5/3.3V design and provides four software controllable power-saving modes. This device is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can be executed in any order for increased performance, but, the 603R makes completion appear sequential. It integrates five execution units and is able to execute five instructions in parallel. Test Pattern to include: * Utilize the entire RISC instruction set * Write/Read to 100% of registers (if applicable) * Verify superscalar instruction handling * Verify Full power, Doze, Nap, and Sleep modes including interrupts and wake ups * Verify Single/Double precision float units * JTAG communication * fINT and fBUS max frequency

Keyword: Software Development

Embedded Application Firmware Assembly Language C Microprocessor